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| CUSTOMER PROCUREMENT SPECIFICATION Z80230 ESCCTM ENHANCED SERIAL COMMUNICATION CONTROLLER GENERAL DESCRIPTION The Zilog Enhanced Serial Communications Controller, Z80230 ESCC, is a pin and software compatible CMOS member of the SCC family introduced by Zilog in 1981. The ESCC is a dual-channel, full-duplex data communications controller capable of supporting a wide range of popular protocols. The ESCC is built from Zilog's industry standard SCC core and is compatible with designs using Zilog's SCC to receive and transmit data. It has many improvements that significantly reduce CPU overhead. The addition of a 4-byte transmit FIFO and an 8-byte receive FIFO significantly reduces the overhead required to provide data to, and get data from, the transmitters and receivers. The ESCC also has many features that improve packet handling in SDLC mode. The ESCC will automatically: transmit a flag before the data, reset the Tx Underrun/EOM latch, force the TxD pin high at the appropriate time when using NRZI encoding, deassert the /RTS pin after the closing flag, and better handle ABORTed frames when using the 10x19 status FIFO. The combination of these features along with the deeper data FIFOs significantly simplifies SDLC driver software. The CPU hardware interface has been simplified by relieving the databus setup time requirement and supporting the software generation of the interrupt acknowledge signal (INTACK). These changes allow an interface with less external logic to many microprocessor families while maintaining compatibility with existing designs. I/O handling of the ESCC is improved over the SCC with faster response of the /INT and /DTR//REQ pins. The many enhancements added to the ESCC permits a system design that increases overall system performance with better data handling and less interface logic. Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS DC-4021-05 (7-07-92) 1 GENERAL DESCRIPTION (Continued) AD1 AD3 AD5 AD7 /INT IEO IEI /INTACK VCC /W//REQA /SYNCA /RTxCA RxDA /TRxCA TxDA /DTR//REQA /RTSA /CTSA /DCDA PCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 AD0 AD2 AD4 AD6 /DS /AS R//W /CS0 CS1 GND /W//REQB /SYNCB /RTxCB RxDB Z80230 30 29 28 27 26 25 24 23 22 21 IEO IEI /INTACK VCC /W//REQA /SYNCA /RTxCA RxDA /TRxCA TxDA NC /INT AD7 AD5 AD3 AD1 AD0 AD2 AD4 AD6 /DS /AS 1 44 43 42 41 40 39 38 37 36 35 Z80230 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 7 8 9 10 11 12 13 14 15 16 17 R//W /CS0 /CS1 NC GND /W//REQB /SYNCB /RTxCB RxDB /TRxCB TxDB NC /DTR//REQA /RTSA /CTSA /DCDA PCLK /DCDB /CTSB /RTSB /DTR//REQB /TRxCB TxDB /DTR//REQB RTSB /CTSB /DCDB Z80230 PLCC Pin Assignments Z80230 DIP Pin Assignments 2 NC ABSOLUTE MAXIMUM RATINGS VCC Supply Voltage range ......................... -0.3V to +7.0V Voltages on all pins with respect to GND ........................ -0.3V to VCC +0.3V Operating Ambient Temperature......................... See Ordering Information Storage Temperature ............................ -65C to +150C Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. STANDARD TEST CONDITIONS The DC Characteristics and capacitance sections below apply for the following standard test conditions, unless otherwise noted. All voltages are referenced to GND. Positive current flows into the referenced pin. +5V Standard conditions are as follows: s s s +4.50 V VCC + 5.50 V GND = 0 V TA as specified in Ordering Information +5V 2.1 K 2.2 K From Output Under Test From Output 100 pf 250 A 50 pf Standard Test Load Open-Drain Test Load CAPACITANCE Symbol CIN COUT CI/O Parameter Input Capacitance Output Capacitance Bidirectional Capacitance Min Max 10 15 20 Unit pF pF pF Test Condition Unmeasured pins returned to ground. Note: f = 1 MHz, over specified temperature range. MISCELLANEOUS Gate Count - 11,000 3 DC CHARACTERISTICS Z80230 Symbol VIH VIL VOH1 VOH2 VOL IIL IOL ICC1 Parameter Input High Voltage Input Low Voltage Output High Voltage Output High Voltage Output Low Voltage Input Leakage Output Leakage VCC Supply Current Min 2.2 -0.3 2.4 VCC-0.8 Typ Max VCC+0.3 0.8 Unit V V V V V A A mA mA mA mA mA Condition 0.4 10.0 10.0 10 (8.5 MHz) 12 (10 MHz) 15 (16 MHz) 20 (20 MHz) IOH = -1.6mA IOH = -250A IOL = +2.0mA 0.4 Crystal OSC Current 4 5 7 9 6 Notes: [1] VCC = 5V 10% unless otherwise specified, over specified temperature range. [2] Typical ICC was measured with oscillator off. [3] No ICC(osc) max is specified due to dependency on the external circuit. 4 AC CHARACTERISTICS Z80230 Read and Write Timing Diagrams /AS 1 2 /CS0 3 4 CS1 5 14 6 /INTACK 7 8 R//W Read 9 10 R//W Write 11 10 /DS 12 13 18 AD7-AD0 Write 15 16 17 20 AD7-AD0 Read 15 16 22 24 19 21 23 /W//REQ Wait 25 /W//REQ Request 26 /DTR//REQ Request 27 /INT 28 PCLK 40 42 41 43 44 Z80230 Read/Write Timing Diagram 5 /AS 7 /INTACK 8 /DS 29 19 30 20 AD7-AD0 Active 31 32 Valid 22 33 IEI 34 35 IEO 36 /INT Z80230 Interrupt Acknowledge Timing Diagram /AS 37 38 35 /DS Z80230 Reset Timing Diagram 6 AC CHARACTERISTICS Z80230 Read/Write Timing Table 10 MHz Min Max 30 10 0 20 50 20 10 125 50 0 0 20 125 4TcPc 10 20 10 0 0 0 120 190 35 210 160 160 4TcPc 500 225 125 80 0 90 175 450 15 15 100 40 10 10 75 26 50 75 70 50 0 45 80 200 [6] [4] 16 MHz Min Max 20 10 0 15 35 10 10 100 30 0 0 15 80 4TcPc 10 10 10 0 0 0 70 110 20 100 60 60 4TcPc 175 [2] [1] [1] No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol TwAS TdDS(AS) TsCSO(AS) ThCSO(AS) TsCS1(DS) ThCS1(DS) TslA(AS) ThlA(AS) TsRWR(DS) ThRW(DS) TsRWW(DS) TdAS(DS) TwDSl TrC TsA(AS) ThA(AS) TsDW(DS) ThDW(DS) TdDS(DA) TdDSr(DR) TdDSf(DR) TdAS(DR) TdDS(DRz) TdA(DR) TdDS(W) TdDSf(REQ) TdDSr(REQ) TdAS(INT) TdAS(DSA) TwDSA TdDSA(DR) TslEl(DSA) ThlEl(DSA) TdlEl(IEO) TdAS(IEO) TdDSA(INT) TdDS(ASQ) TdASQ(DS) TwRES TwPCl Parameter /AS Low Width /DS Rise to /AS Fall Delay /CS0 to /AS Rise Setup Time /CS0 to /AS Rise Hold Time CS1 to /DS Fall Setup Time CS1 to /DS Rise Hold Time /INTACK to /AS Rise Setup Time /INTACK to /AS Rise Hold Time R//W (Read) to /DS Fall Setup Time R//W to /DS Rise Hold Time R//W (Write) to /DS Fall Setup Time /AS Rise to /DS Fall Delay /DS Low Width Valid Access Recovery Time Address to /AS Rise Setup Time Address to /AS Rise Hold Time Write Data to /DS Fall Setup Time Write Data to /DS Rise Hold Time /DS Fall to Data Active Delay /DS Rise to Read Data Not Valid Delay /DS Fall to Read Data Valid Delay /AS Rise to Read Data Valid Delay /DS Rise to Read Data Float Delay Address Required Valid to Read Data Valid Delay /DS Fall to Wait Valid Delay /DS Fall to /W//REQ Not Valid Delay /DS Fall to /DTR//REQ Not Valid Delay /AS Rise to /INT Valid Delay /AS Rise to /DS Fall (Acknowledge) Delay /DS (Acknowledge) Low Width /DS Fall (Acknowledge) to Read Data Valid Delay IEI to /DS Fall (Acknowledge) Setup Time IEI to /DS Rise (Acknowledge) Hold Time IEI to IEO Delay /AS Rise to IEO Delay /DS Fall (Acknowledge) to /INT Inactive Delay /DS Rise to /AS Fall Delay for No Reset /AS Rise to /DS Fall Delay for No Reset /AS and /DS Coincident Low for Reset PCLK Low Width Notes* [1] [1] [1] [1] [1] [3] [4] [4] [5] [7] 1000 100 7 AC CHARACTERISTICS Z80230 Read/Write Timing Table (Continued) 10 MHz Min Max 40 100 1000 2000 10 10 16 MHz Min Max 26 61 1000 2000 5 5 No 41 42 43 44 Symbol TwPCh TcPC TrPC TfPC Parameter PCLK High Width PCLK Cycle Time PCLK Rise Time PCLK Fall Time Notes* Notes: [1] Parameter does not apply to Interrupt Acknowledge transactions. [2] Parameter applies only between transactions involving the SCC. [3] Float delay is defined as the time required for a 0.5V change in the output with a maximum DC load and a minimum AC load. [4] Open-drain output, measured with open-drain test load. [5] Parameter is system dependent. For any Z-SCC in the daisy chain. TdAS(DSA) must be greater than the sum of TdAS(IEO) for the highest priority device in the daisy chain. TslEl(DSA) for the Z-SCC, and TdlElf(IEO) for each device separating them in the daisy chain. [6] Parameter applies only to a Z-SCC pulling INT Low at the beginning of the Interrupt Acknowledge transaction. [7] Internal circuitry allows for the reset provided by the Z8 to be recognized as a reset by the Z-SCC. All timing references assume 2.0V for a logic "1" and 0.8V for a logic "0". * Units in nanoseconds (ns). 8 AC CHARACTERISTICS Z80230 General Timing Diagram PCLK 1 /W//REQ Request 2 /W//REQ Wait 3 /CTS//TRxC, RTxC Receive 4 5 6 7 RxD 8 9 /SYNC External 10 /CTS//TRxC, RTxC Transmit 11 12 TxD 13 /CTS//TRxC Output 14 15 /RTxC 16 17 /CTS//TRxC 18 20 19 /CTS//TRxC, /DCD 21 21 /SYNC Input 22 22 Z80230 General Timing Diagram 9 AC CHARACTERISTICS Z80230 General Timing Table 10 MHz Min Max 200 300 NA 0 125 0 125 -150 5TcPc NA 150 150 140 120 120 400 50 100 120 120 400 120 120 1000 80 80 244 31 100 80 80 244 70 70 1000 NA 0 60 0 60 -100 5TcPc NA 85 85 80 [6] [6] [6,7] [7,8] [3] [6] [6] [6,7] 16 MHz Min Max 110 180 [1,4] [1] [1] [1,5] [1,5] [1] [1] [2,4] [2] [2,5] No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16a 16b 17 18 19 20 21 22 Symbol TdPC(REQ) TsPC(W) TsRXC(PC) TsRXD(RXCr) ThRXD(RxCr) TsRXD(RXCf) ThRXD(RXCf) TsSY(RXC) ThSY(RXC) TsTXC(PC) TdTXCf(TXD) TdTxCr(TXD) TdTXD(TRX) TwRTXh TwRTXl TcRTX TxRX(DPLL) TcRTXX TwTRXh TwTRXl TcTRX TwEXT TwSY Parameter /PCLK Low to W/REQ Valid /PCLK Low to Wait Inactive /RxC High to /PCLK High Setup Time RxD to /RxC High Setup Time RxD to /RxC High Hold Time RxD to /RxC Low Setup Time RxD to /RxC Low Hold Time SYNC to /RxC High Setup Time SYNC to /RxC High Hold Time /TxC Low to /PCLK High Setup Time /TxC Low to TxD Delay /TxC High to TxD Delay TxD to TRxC Delay RTxC High Width TRxC Low Width RTxC Cycle Time DPLL Cycle Time Min Crystal Osc. Period TRxC High Width TRxC Low Width TRxC Cycle Time DCD or CTS Pulse Width SYNC Pulse Width Notes* Notes: [1] RxC is /RTxC or /TRxC, whichever is supplying the receive clock. [2] TxC is /TRxC or /RTxC, whichever is supplying the transmit clock. [3] Both /RTxC and /SYNC have 30 pf capacitors to ground connected to them. [4] Synchronization of RxC to PCLK is eliminated in divide by four operation. [5] Parameter applies only to FM encoding/decoding. [6] Parameter applies only for transmitter and receiver; DPLL and baud rate generator timing requirements are identical to case PCLK requirements. [7] The maximum receive or transmit data rate is 1/4 PCLK. [8] Applies to DPLL clock source only. Maximum data rate of 1/4 PCLK still applies. DPLL clock should have a 50% duty cycle. * Units in nanoseconds (ns). 10 AC CHARACTERISTICS Z80230 System Timing Diagram /RTxC, /TRxC Receive /W//REQ Request 1 /W//REQ Wait 2 /SYNC Output 3 /INT 4 /TRxC, /RTxC Transmit /W//REQ Request 5 /W//REQ Wait 6 /DTR//REQ Request 7 /INT 8 /CTS, /DCD /SYNC Input 9 /INT 10 Z80230 System Timing Diagram 11 AC CHARACTERISTICS Z80230 System Timing Table 10 MHz Min Max 13 13 4 13 2 11 8 9 7 +2 2 +2 2 17 19 7 17 3 14 14 12 9 +3 6 +3 3 16 MHz Min Max 13 13 4 13 +2 11 8 9 7 +2 2 +2 3 17 19 7 17 +3 14 14 12 9 +3 6 +3 8 No 1 2 3 4b 5 6 7 8b 9 Symbol TdRXC(REQ) TdRXC(W) TdRdXC(SY) TdRXC(INT), Z80230 TdTXC(REQ) TdTXC(W) TdTXC(DRQ) TdTXC(INT), Z80230 TdSY(INT) Parameter /RxC High to W/REQ Valid /RxC High to Wait Inactive /RxC High to SYNC Valid /RxC High to INT Valid /TxC Low to W/REQ Valid /TxC Low to Wait Inactive /Txc Low to DTR/REQ Valid /TxC Low to /INT Valid SYNC to INT Valid Notes* [2] [1,2] [2] [1,2] [4] [3] [1,3] [3] [1,3] [4] [1] [4] [1,4] 10b TdEXT(INT), Z80230 Notes: * Units equal to TcPc. [1] Open drain-output, measured with open-drain test load. [2] /RxC is /RTxC or /TRxC, whichever is supplying the receive clock. [3] /TxC is /TRxC or /RTxC, whichever is supplying the transmit clock. [4] Units equal to /AS. 12 |
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